Intel's CTO: current tools can only double leading-edge chip production, while AI demand grows 3x a year

This article is the blog post for a podcast episode. Its author spent two days at Intel's most advanced factory and spoke with its technical leadership to understand what the chips of the future will look like. It is a new format for the podcast, with animations explaining gate-all-around, backside power delivery, CFET and hybrid bonding. A note on this summary: the text received cuts off mid-conversation, just as the section on High-NA EUV begins. What follows covers only the introduction and the first sections. Left out are the sections on ruthenium, stacked transistors, hybrid bonding, competition with TSMC and Terafab, which do appear in the page's table of contents.

The central thesis is in the introduction. AI compute has been growing 3x a year for a decade. According to Intel's CTO, the current global fleet of chipmaking tools could only double production of leading-edge wafers. That gives rise to the episode's question: what tricks can foundries use to delay the point at which demand clearly outstrips supply. The text also notes that production is constrained by equipment Intel buys from suppliers, above all ASML's EUV machines. The video cites statements from industry executives describing enormous AI demand. One puts it at 40% to 50% above maximum capacity, something the executive says he has never seen before.

The first conversation is with Chris Auth, who leads development of the processes already in manufacturing. He explains that the 14A node has been in development for about three years or more and that the process and the toolset it will be manufactured with are now being finalized. According to him, the fab involves about 2,000 steps, and each must be tuned to produce thousands of wafers per week repeatably. To improve yield, Intel detects defects in two ways. One is inline metrology, with tools that inspect wafers during the process. The other is electrical testing or sorting at the end of the line. Failures are then analyzed with cross-sections in the transmission electron microscopy (TEM) lab. The cross-section shows which layers the defect lies between and, therefore, where in the flow it originated. The lesson Auth repeats is not to pack too much innovation into a single node, because complexity grows and a predictable schedule must be met for the customer.

That approach stems from the experience with the 10-nanometer node. Its launch was planned for 2016 and manufacturing did not begin until 2018. Auth explains that the company bet on very aggressive scaling, called "hyperscaling," without new tools because they were not yet ready. That placed a heavy burden on the process and the engineers. Even so, he says 10 nm ended up being a great technology in yield, performance and cost, although it took longer than desired. He points to EUV lithography as the technology that probably should have been left for later. When 10 nm was defined, it was concluded that EUV was not ready. According to the article, TSMC adopted it earlier: volume production in 2019 and expansion on its 5 nm node in 2020. Intel's first EUV products arrived in 2023, so TSMC accumulated about four more years of experience with these machines. Since then Intel has used maturity criteria and a "phase gate" process. To move from exploration to development, yield, defect and performance requirements must be met. Anything that does not meet them is deferred to the next node.

The article then includes an explainer on the evolution of the transistor. A transistor is a switch between source and drain, controlled by a gate. As sizes shrank, current leakage appeared. The solution was for the gate to surround the channel on more sides. In the planar transistor, demonstrated in 1960, the gate touches the channel only from above. In the FinFET it touches three sides, because the channel is a vertical fin. In gate-all-around (GAA) it surrounds it completely, and the channel is split into thin sheets. Manufacturing GAA requires new materials and steps. The sheets are interleaved with layers of a sacrificial material, which is later removed. They are then coated with a "high-k" insulator and the gate metal is added. The text gives these dates. The FinFET was demonstrated in the lab in 1989 and reached production at Intel in 2011. GAA was demonstrated in 1988, but Samsung did not begin producing it until 2022. Between the two there is a gap of about ten years in reaching the fab.

Auth explains that delay with the principle of not tackling a problem before you have to. While other performance levers were available, such as strained silicon, high-k metal gate and FinFETs, it was not worth taking on the difficulties of GAA, which he describes as the "ultimate transistor." Integrating high-k with GAA requires invention, new materials and different tools, and suppliers often have to develop new equipment. On how R&D has changed, he contrasts the 1980s and 1990s, dominated by Dennard scaling and lithography, with the period since the 2000s. He calls it a "golden age of innovation," with strained silicon, high-k, FinFET, GAA and backside power delivery. He estimates the number of materials used has increased roughly tenfold since the 1990s. He also mentions atomic layer deposition, which allows the process to be controlled atom by atom.

The last part received deals with High-NA EUV lithography, which Intel uses in 14A. It keeps the same extreme ultraviolet light but changes the optics. The numerical aperture goes from 0.33 to 0.55, allowing features about 1.7 times smaller to be printed in a single pass. If that is not possible, the pattern must be split into several passes, with more machine time and greater risk of defects. According to the article, an EUV machine costs about $200 million and High-NA machines cost roughly twice that. Auth explains that Intel and TSMC draw different conclusions from the same tools. Intel uses backside power delivery, which relaxes pitch requirements on the front side and allows direct printing with High-NA. TSMC, without it, needs tighter pitches and relies on double patterning with standard EUV, so High-NA is less useful to it. Auth adds that in 14A, High-NA has been left as an option to be discussed with the customer, because it adds value but also complexity.

Overall, the available portion leaves a clear idea. Advances in transistors and lithography arrive after long maturation periods, and manufacturers prioritize predictable schedules. AI demand is growing much faster than tool capacity, according to the figure Intel's CTO gives in the introduction. The detail behind that claim, that is, why the tools are not enough to increase production tenfold and what options exist, belongs to a section that could not be read in the material received.