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← Back to the day · September 17, 2026

TeRAM emerges from stealth with $37 million to tackle AI's 'memory wall' with 3D SRAM

🕒 Published on Zendoric: September 17, 2026 · 08:28

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Important notice before getting into the substance: this text is, according to its own label on the source page ('This is a paid press release. Contact the press release distributor directly with any enquiries'), a paid press release, not a piece of independent journalism.

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An important caveat before getting into the details: this text is, according to its own label on the source page ('This is a paid press release. Contact the press release distributor directly with any enquiries'), a paid press release, not a piece of independent journalism. That means the claims, figures and assessments it contains come solely from the company itself and its investors, without external verification or journalistic scrutiny. The summary that follows sticks strictly to what that release says.

TeRAM, a startup based in Los Altos, California, has announced its emergence from stealth mode with a $37 million equity funding round from early-stage investors. According to the release, the round closed on September 10, 2026, and was co-led by Primary Venture Partners, B Capital, Hyperion and SemiAnalysis Capital, with additional participation from Alumni Ventures and Lightscape Partners.

The company's stated goal is to develop custom 3D SRAM memory for frontier artificial intelligence applications, starting with data centers. The company argues that as AI models surpass two trillion parameters (following the logic of so-called 'scaling laws,' according to which models become more capable the larger their parameter counts and context windows), new memory technology is needed to increase capacity and performance while reducing energy consumption. TeRAM says it is validating its technology with the goal of reaching production for its first customers in 2029.

The release's central technical argument is the so-called 'memory wall.' According to the company, since mid-2025 agentic inference (that is, the use of AI models in autonomous or semi-autonomous workflows) has overtaken training as the main driver of AI compute consumption and token generation. This shift, TeRAM argues, has moved the bottleneck: where the problem used to be HBM (High Bandwidth Memory) capacity during model training, the problem now is memory bandwidth during the inference phase. The reason the release gives is that generating each output token requires traversing the entire model and its trillions of parameters, which makes memory bandwidth a limiting factor, whether the model resides in SRAM integrated on the chip itself or in external HBM modules.

TeRAM's technical answer consists of developing memory and packaging technologies that allow 3D SRAM to be integrated directly on top of AI compute chips, designed to withstand demanding thermal conditions. According to the company, the goal is to deliver unprecedented memory bandwidth with the lowest possible power consumption, and to tailor capacity, bandwidth, form factor and packaging to each customer's specific needs, from data centers to small edge devices.

As for the team, the release notes that TeRAM's founders collectively have more than 80 years of experience developing semiconductor memory technology, and that they have previously collaborated on system-on-chip (SoC) projects for AI compute alongside several hyperscalers and AI infrastructure companies, without those partners being identified by name. That combination of memory and compute experience is, according to the company, what enables it to understand the challenges of future AI platforms.

TeRAM CEO Charlie Cheng thanked investors in the release for their confidence and noted that developing a new memory technology is an ambitious undertaking. For his part, Brian Schechter, a partner at Primary Venture Partners and lead investor in the seed round, described memory as the main constraint on AI progress and said incremental improvements will not be enough, calling Cheng a founder capable of bridging AI architecture, memory physics and semiconductor manufacturing.

Beyond these details, the release offers no further information about the company's valuation, headcount, concrete technical specifications (such as memory capacities in gigabytes or bandwidth figures), or about deals already signed with data center customers. Nor is there, since this is a paid press release, any independent assessment of the technical or commercial viability of the proposal, so the announcement is best treated as the public presentation of an investment thesis and a technology roadmap, rather than a milestone already validated by the market.

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