IBM stacks transistors upward: the 'nanostack' chip that promises ten more years of progress

For half a century, the progress of computing rested on a single repeated gesture: making transistors smaller. Moore's Law was never a physical law, but an industry promise fulfilled by shrinking switches every two years. The trouble is that this promise long ago ran into a wall of quantum physics: below certain dimensions, electrons stop behaving predictably. IBM's June 25 announcement, reported by Sophia Chen in MIT Technology Review, does not break that wall; it goes around it with an idea as old as urban planning. If there is no land left, you build upward.

The architecture, internally dubbed 'nanostack,' stacks layers of transistors on top of one another within the same silicon chip using CFET (complementary field-effect transistor) technology. The process, described by the company as a layer cake, fabricates one floor of transistors, deposits silicon on top, raises the next floor and connects the two electrically. The most ingenious detail is that the two layers are not exactly superimposed, but staggered: that lateral offset, according to IBM, simplifies the internal wiring and eases manufacturing. Qing Cao, of the University of Illinois, stresses that the real leap lies not in the concept—others already stack—but in achieving it across a full wafer on an advanced production line, and not in a lab sample.

A little terminological hygiene, which the article itself welcomes, is in order. The '0.7 nanometers' label is marketing, not measurement: the distance between transistors has been stable for some time at around 40 nanometers. What is physically verifiable is the fineness of the channels through which the electrons flow, formed by three sheets of silicon fifteen atoms thick and separated by nine nanometers. Distinguishing the commercial figure from the real data is not pedantry: it is the difference between understanding the technology and buying the slogan.

The performance figures IBM offers—up to 50% more work in the same time and up to 70% greater energy efficiency compared with its previous architecture—are, for now, manufacturer promises that will have to be confirmed in commercial silicon. But the most interesting angle is energy. Jay Gambetta, director of IBM Research, places mass deployment in data centers within a decade, and there efficiency stops being a catalog metric and becomes a necessity. With computing demand for AI soaring, every watt saved per transistor is a real lever on the electricity bill and the environmental footprint of the infrastructure.

One key point deserves caution: IBM is presenting a prototype and announcing that it will seek manufacturing partners for mass production. The technology historian knows that between the working demonstration and the chip that reaches the market lies a stretch full of yield, cost and scaling problems. That Intel, Samsung and TSMC are pursuing the same direction confirms that the vertical path is the industry consensus, but it also serves as a reminder that IBM is competing to lead a transition, not to monopolize it.

Dan Hutcheson, of TechInsights, calls it 'transformative' and speaks of 'another ten or fifteen years on the roadmap.' Even discounting an analyst's natural enthusiasm, the underlying idea is solid and frankly encouraging: progress in semiconductors is not over, it has simply shifted axes. Engineering's creativity has once again found a way out where physics seemed to close the door. And that, for an industry that has lived under the shadow of Moore's end for years, is news that invites measured optimism.